SC4624MLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC4624MLTRT
Semtech Corporation
'SC4624MLTRT' PDF : 20 Pages View PDF
SC4624
POWER MANAGEMENT
OAppelriactaiotinon Information (Cont.)
145
135
125
115
105
95
85
75
65
55
45
35
25
15
5
200
Switching Frequency Setting
5VIN
2.5VIN
400
600
800 1000 1200 1400 1600 1800 2000
FOSC (kHz)
Figure 15. Switching Frequency vs. RFS
The operation frequency can be programmed up to 2MHz,
but there is a minimum on-time limitation which is around
110ns. Users should take care of minimum limitation
on the operating duty cycle under high frequency
application.
Synchronization Frequency
Synchronization operation mode is invoked by using an
external clock signal and is activated when the SYNC/EN
is pulled and held above 2V and held below 0.8V. The
range of synchronization frequency is from 200kHz to
2MHz.
Thermal Shutdown
When the junction temperature rises up around 160°C,
the internal soft start voltage is held low, the internal high
side and low side MOSFETs are turned off and the output
voltage will fall to zero. Once the junction temperature
goes below hysteresis temperature around 10°C, the
regulator will restart. (refer to Figure 8).
Linear Mode Operation (100% duty)
The SC4624 can allows 100% duty cycle operation. The
Vout is,
9287 9,1 5/ 5 '6+ u ,287
where
RRDLS:HO:uItnptuertninadl uhcigthorsDidCe
resistance.
P-MOSFET
resistance.
(refer to Figure11).
As Vin drops gradually and close to Vout, the buck regulator
will go into 100% duty cycle ratio. A matter needing
attention is internal high side PMOS has minimum off time
limitation and is related to duty cycle rate. This condition
makes the working duty cycle perform at randon with the
output ripple increasing and a poor transient response.
Above phenomenon can be improved by larger output
capacitor and smaller output inductor. Users need to
verify whether above application condition has opposite
influence on entire circuit.
A jitter happens when sync pulse clock edge is less than
120ns before the phase switches. It is caused by the
ground bounce of synchronization pulse coupled to PWM
comparator. Users try to avoid this application. (refer to
Figure 9).
Power Good Indicator
The PGOOD pin is an open-drain and incorporated window
comparators output. It’s is necessary that a pull-up
resistor from the PGOOD pin to the input supply for setting
the logic high level of the PGOOD signal. When FB voltage
is within +10% setting output voltages typical, the output
of power good comparator becomes high impedance after
delay time. The PGOOD signal delay time is around 1024/
FOSC. In shutdown mode the power good output is actively
pulled low.
For example, 1MHz switching frequency applications, the
PGOOD delay time is around 1ms.
Over Current Protection
A over current setting is programmed by an external
resistor (RISET). It goes through internal sense resistor and
generates a voltage.
9
9 , u 5 FF
2QVHQVH
where
I : The current is generated by RISET , and it is amplified
by internal current amplifier.
RONSENSE : Internal sense resistor.
Output inductor current goes through internal high side
P-MOSFET and generate a voltage.
9 9 , u 5 ,1
/
'6+ 21
where
IL : Output inductor current.
RDSH(ON) : High side P-MOSFET conduction resistance.
2008 Semtech Corp.
12
www.semtech.com
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