SC486
POWER MANAGEMENT
Design Procedure (Cont.)
Secondly calculating the value of CTOP required to achieve
this:
calculated by substituting the desired current for the I
OUT
term.
For our DDR2 VDDQ example:
C TOP
=
Z
1
TOP
1
− RTOP
2 • π • fSW _ VBAT(MIN)
F
For our DDR2 VDDQ example we will use RTOP = 4.64kΩ
and RBOT = 23.2kΩ, therefore
VFB_VBAT(MIN) = 16.7mVP-P - good
No additional capacitance is required, however a no-pop
space is recommended to allow for adjustment once the
design is complete, laid out and built.
Next we need to calculate the minimum output
capacitance required to ensure that the output voltage
does not exceed the transient maximum limit, POSLIMTR,
starting from the actual static maximum, V , OUT_ST_POS when
a load release occurs:
VOUT _ ST _POS = VOUT + ERRDC V
For our DDR2 VDDQ example:
VOUT_ST_POS = 1.836V
POSLIMTR = VOUT • TOL TR V
Where TOLTR is the transient tolerance. For our DDR2
VDDQ example:
POSLIM = 1.900V
TR
The minimum output capacitance is calculated as
follows:
COUT(MIN) = 839µF.
We will select 440µF, using two 220µF, 15mΩ
capacitors in parallel, which will be good for load release
steps of up to 6.7A.
Next we calculate the RMS input ripple current, which is
largest at the minimum battery voltage:
I = IN(RMS)
( ) V • V − V OUT
BAT ( MIN )
OUT
IOUT
• V A BAT _MIN
RMS
For our DDR2 VDDQ example:
IIN(RMS) = 4ARMS
Input capacitors should be selected with sufficient ripple
current rating for this RMS current, for example a 10µF,
1210 size, 25V ceramic capacitor can handle
approximately 3ARMS. Refer to manufacturer’s data
sheets.
Finally, we calculate the current limit resistor value. As
described in the current limit section, the current limit
looks at the “valley current”, which is the average output
current minus half the ripple current. We use the
maximum room temperature specification for MOSFET
RDS(ON) at VGS = 4.5V for purposes of this calculation:
I = I − I 2 A VALLEY
OUT
RIPPLE _ VBAT(MIN)
The ripple at low battery voltage is used because we want
to make sure that current limit does not occur under
normal operating conditions.
( ) COUT(MIN)
=L•
IOUT
+
IRIPPLE _ VBAT(MAX)
2
2
POSLIM TR 2
−
V2
OUT _ ST _ POS
F
( ) RILIM
=
IVALLEY
• 1.2
•
RDS(ON) • 1.4
10 • 10−6
Ohms
For
our
DDR2
VDDQ
example
R
DS(ON)
=
9mΩ:
This calculation assumes the absolute worst case
condition of a full-load to no load step transient occurring
when the inductor current is at its highest. The
capacitance required for smaller transient steps my be
IVALLEY = 8.69A and RILIM = 13.1kΩ
We select the next lowest 1% resistor value: 13.0kΩ
2006 Semtech Corp.
17
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