POWER MANAGEMENT
Layout Guidelines (Cont.)
Next looking at the VTT output:
VTT
VDDQ
C 15
10u
C 16
10u
C 17
1u
U1
11 VTTEN
3 VDDQS
2 TON
6 FB
8 REF
9 COMP
10 VTTS
5 VCCA
4 VSSA
14
15
VTT
VTT
12
13
VTTI N
VTTI N
16
17
PGN D 2
PGN D 2
SC486
PGD 7
EN/PSV 1
BST 24
DH 23
ILIM 21
LX 22
DL 19
VDDP 20
PGND1 18
SC486
Figure 13: VTT Output
The output capacitors should be connected right at the chip, on the same side as the chip and right across the pins.
The input capacitor may be placed on the opposite side, if desired. See Figure 14 below:
Figure 14: Example VTT Output Component Placement and Starred Ground
Output capacitors C15 and C16 are placed across the device pins, and connect to the ground plane using multiple
vias. Input capacitor C17 connects directly to the device pins and connects to the ground plane using two vias. Note
that PGND1, PGND2 and VSSA all connect to the pad under the device, which should also connect to the ground
plane using multiple vias.
2006 Semtech Corp.
24
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