SC5010
Applications Information (continued)
for R9 and C6 should be PGND. These components
should be close to the SC5010.
5. Resistor (R8) is the output current adjusting resistor
for IO1 through IO8 and should return to AGND. Place
it next to the IC.
6. Resistor (R6) is the switching frequency adjusting
resistor and should return to AGND. Place it next to
the IC.
7. The decoupling capacitor (C3) for Pin BG should return
to AGND. Place it next to the IC.
8. Resistors (R4, R5) form a divider to set the SCP level, R4
should return to AGND. Place it next to the IC.
9. Resistors (R2, R1) form a divider to set the UVLO level
for V . R1 should return to AGND. Place it next to the
IN
IC.
10. R11 and R10 form a divider to set the OVP level for
VOUT, R10 should return to AGND. Place it next to the
IC.
11. All the traces for components with AGND connection
should avoid being routed close to the noisy areas.
12. An exposed pad is located at the bottom of the SC5010
for heat dissipation. A copper area underneath the
pad is used for better heat dissipation. On the bottom
layer of the PCB another copper area, connected
through vias to the top layer, is used for better
thermal performance. The pad at the bottom of the
SC5010 should be connected to AGND. AGND should
be connected to PGND at single point for better noise
immunity.
Vin
(5-27V)
PGND
Vcc (5V)
AGND
C1
4 . 7 μF
R2
30K
C2
2 . 2 μF
R1
10K
Q2
L1
C7
10nF
D1
Q1
R9
0.1
U1 28 27 26 25 24 23 22
R11
C6
R10
Vout
R3
10K
R4
R5
C3
1 μF
R6
100k
1
VCC
2 EN
3 UVLO
4
SCP
5 BG
6
FSET
7
AGND
S C5010
IO2 21
IO3 20
IO4 19
18
IO5
IO6 17
IO7 16
IO8 15
R15
20K
8 9 10 11 12 13 14
R7
C4
C5
THP
PAD
R8
SYNC SCL SDA
FLT PWMI
Vcc (5V)
Figure 4 — Cascode Configuration (for high output voltage application)
23