SC5010H
Definition of Registers and Bits (continued)
Device Control Register
This register provides different control features of the device.
Bit Field
0x01 [7:6]
0x01 [5]
0x01 [4]
0x01 [3]
0x01 [2]
0x01 [1]
0x01 [0]
Definition Read / Write Description
WIN[1:0]
A modified duty cycle sent into the PWMI pin replaces the existing saved duty cycle when its
deviation from the saved duty is outside the window for two consecutive samples.
00 = 0 bits (no window)
R/W
01 = ±1 bit window
10 = ±2 bit window
11 = ±3 bit window
FAST_FREQ
Determines the LED PWM dimming frequency selection:
0 = Low PWM dimming frequency mode assuming 10-bit PWM duty cycle dimming, dividing
R/W
the system clock 10MHz / (1024 x (FREQ+1)).
1 = High PWM dimming frequency mode assuming 9-bit PWM duty cycle dimming, dividing
the system clock 10MHz / (512 x (FREQ+1)).
FLT_EN
This bit enables fault checking:
R/W
0 = LED_OPEN and LED_SHORT faults are not checked.
1 = LED_OPEN and LED_SHORT faults are checked.
SYNC_EN
Enables video signal synchronization with the PLL:
R/W
0 = SYNC is disabled.
1 = PLL tracks the SYNC input signal.
PH_SHIFT
Enables String-by-String phase shifting. This is a don’t care if INT_PWM=0.
R/W
0 = Phase shifting disabled.
1 = Phase shifting is enabled
INT_DUTY
Determines the duty cycle source. This is a don’t care if INT_PWM = 0.
R/W
0 = LED duty cycle is set by the PWMI input
1 = LED duty cycle is set by the 10-bit duty cycle control registers
INT_PWM
Sets the LED PWM dimming source.
0 = LED PWM dimming driven directly from the PWMI input source (direct PWM dimming)
R/W
1 = LED PWM dimming driven from an internal oscillator (required for phase-shifted PWM
dimming); enables the PLL.
31