SC5010H View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC5010H
Semtech Corporation
'SC5010H' PDF : 36 Pages View PDF
SC5010H
Definition of Registers and Bits (continued)
Analog Dimming Control Register
This register is used to program the LED string current through the on-chip 5-bit DAC.
Bit Field
0x02 [4:0]
Definition Read / Write Description
IDAC [4:0]
R/W
5-bit analog dimming register — The LED string current can be evenly adjusted in 32 steps
from 0mA to the maximum value determined by RISET.
For example, if the maximum LED string current set by RISET is 20mA/string, when IDAC[4:0] is
set to be 0b00101, the LED string current will be 20mA x 5/(25-1) = 3.2mA/string.
Dimming Duty Cycle Control Register
These two registers (0x03 and 0x04) combine together as a 10-bit or 9-bit register for controlling the PWM dimming duty
cycle, depending on the value of FAST_FREQ (FAST_FREQ=1, 9-bit; FAST_FREQ=0, 10-bit).
Bit Field Definition Read / Write Description
0x03 [1:0]
0x04 [7:0]
D [9:0]
R/W
PWM brightness setting — This value is spread over registers: 0x03 (MSB portion) and 0x04
(LSB portion). The LED PWM dimming duty cycle can be evenly adjusted by the 10-bit register
from 0 to 100% with D[9:0] value changes from 0 to 0x3FF.
Dimming Frequency Select Register
This register is used to program the LED PWM dimming frequency.
Bit Field
0x05 [7:0]
Definition Read / Write Description
FREQ [7:0]
R/W
This register sets the LED dimming frequency.
FAST_FREQ = 1, then LED dimming frequency is equal to 10MHz / (512 x (FREQ+1))
FAST_FREQ = 0, then LED dimming frequency is equal to 10MHz / (1024 x (FREQ+1))
PLL Control Registers
This register is used to set the PLL divider value.
Bit Field
0x06 [1:0]
0x07 [7:0]
0x08 [7:0]
Definition Read / Write Description
NPLL [17:0]
R/W
These registers set the PLL divider value — The system clock is intended to run at 10MHz; this
value divides the system clock down to a frequency comparable to the SYNC signal’s frequen-
cy to allow PLL synchronization. Typical values are shown below.
FIN
60 Hz
1 MHz
PLL Divider N
169,982
8
Register Values
0x02 - 0x97 - 0xFE
0x00 - 0x00 - 0x08
FPLL = (N+2) × FIN
10MHz
10MHz
32
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