SC900A View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC900A' PDF : 23 Pages View PDF
SC900A
POWER MANAGEMENT
Applications Information (Cont.)
Layout Considerations
Layout is straightforward if you use the Gerber files on
page 21 as a reference. Notice that the input voltage feed
to the SC900A is on the bottom of the board and vias con-
nect this voltage track to the top of the board and then
to the SC900A itself. The input bypass can be one 4.7μF
capacitor, two 3.3μF capacitors, three 2.2μF capacitors or
five 1μF capacitors. The determining factor is how much
copper is available on the input voltage feed track and
how much room is available. If the input voltage track is
very thin, then use five 1μF capacitors placed very close
to the input pins of the SC900A. If the input track is fairly
thick, then you can use a single 4.7μF capacitor at the be-
ginning of the voltage feed track since a wider track has
less inductance per inch. The SC900AEVB has five 1μF
capacitors, but these can be replaced with one 4.7μF in
place of C1 and opens in place of C9, C14, C15, and C16
(see page 20 for details).
LDO Reset Control Logic Table (Defaults are in Bold)
Register
Name
Register
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LDO A
0x00
X
LDO B
LDO C
0x01
0x02
X
Active
Shutdown
1 = ON
0 = OFF
Output Voltage Codes
Table A for LDOs A & B
Table B for LDOs C, D & E
LDO D
0x03
LDO E
LDO Reset
Control
On/Off Control
Register
0x04
0x05
0x06
LDOPGD Pin
ARST Pin
Reset Polarity Bit Reset Polarity Bit
X
X
LDOPGD Monitor Logic Bits
LDOPGD Delay Bits
LDO (A) Reset Delay Bits
X
ON/OFF Control ON/OFF Control ON/OFF Control ON/OFF Control ON/OFF Control
LDO E
LDO D
LDO C
LDO B
LDO A
1
0
1
0
1
0
1
0
1
0
ON OFF ON OFF ON OFF ON OFF ON OFF
LDO Reset Control Logic Table (Defaults are in Bold)
Bit 7
Result
Bit 6
Result
Bit 5
Bit 4
Result
LDOPGD Pin Polarity
0 High: Power Fail
Low: Power Good
1 High: Power Good
Low: Power Fail
ARST Pin Polarity
0 High: Reset
Low: Power Good
1 High: Power Good
Low: Reset
LDOPGD Monitor Logic
0
0
LDOs
A, C, D & E
Good
0
1
LDO E Good
1
0
LDO C Good
1
1
LDO D Good
Bit 3 Bit 2
Result
LDOPGD Delay
0
0
150ms
0
1
100ms
1
0
1
1
50ms
0ms
Note:
Digital outputs are powered from INB, additionally LDOB must be on for operation of LDOPGD and ARST.
Bit 1
0
Bit 0
Result
ARST Delay
0
150ms
0
1
50ms
1
0
1
1
100ms
0ms
SC900A Slave Address
DEVICE TYPE IDENTIFIER
DEVICE ADDRESS
R/W
0
0
0
1
0
0
A0
X
© 2005 Semtech Corp.
12
www.semtech.com
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