SC900A View Datasheet(PDF) - Semtech Corporation
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Description
MFG CO.
'SC900A' PDF : 23 Pages View PDF
SC900A
POWER MANAGEMENT
Applications Information (Cont.)
Using the I2C Interface
The SC900A is a read-write slave mode I2C device and complies with the Philips I2C standard version 2.1 dated January
2000. The SC900A has six user-accessible internal 8-bit registers. The I2C interface has been designed for program
flexibility, in that once the slave address has been sent to the SC900A enabling it to be a slave transmitter/receiver,
any register can be written to or read from independently of each other. While there is no auto increment/decrement
capability in the SC900A I2C logic, a tight software loop can be designed to randomly access the next register indepen-
dent of which register you have been accessing. The start and stop commands frame the datapacket and the repeat
start condition is allowed if necessary.
SC900A Limitations to the I2C Specifications
Seven-bit addressing is required for communication with the SC900A; ten-bit addressing is not allowed. Any general
call address will be ignored by the SC900A. Note that the SC900A is not CBUS compatible. Finally, the SC900A can
operate in standard mode (100kbit/s) or fast mode (400kbit/s).
Supported Formats
Direct Format - Write
The simplest format for an I2C write is the direct format. After the start condition [S], the slave address is sent, followed
by an eighth bit indicating a write. The SC900A I2C then acknowledges that it is being addressed, and the master re-
sponds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the
appropriate 8-bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop
condition [P].
I2C Direct Format - Write
S Slave Address W A Register Address A
Data
AP
S: Start Condition
W: Write = ‘0’
A: Acknowledge (sent by slave)
P: Stop condition
Slave Address: 7 bit
Register Address: 8 bit
Data: 8 bit
Combined Format - Read
After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC900A I2C
then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the reg-
ister address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again the slave
address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previ-
ously addressed 8-bit data byte. The master then sends a non-acknowledge (NACK). Finally the master terminates the
transfer with the stop condition [P].
I2C Combined Format - Read
S Slave Address W A Register Address A Sr Slave Address R A
Data
NACK P
S: Start Condition
Slave Address: 7 bit
W: Write = ‘0’
Register Address: 8 bit
R: Read = ‘1’
Data: 8 bit
A: Acknowledge (sent by slave)
NACK: Non-Acknowledge (sent by master)
Sr: Repeated Start Condition
P: Stop condition
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