SL20T0081 View Datasheet(PDF) - System Logic Semiconductor
Part Name
Description
MFG CO.
'SL20T0081' PDF : 56 Pages View PDF
SLS System Logic Semiconductor
SL20T0081
Data Transfer
The SL20T0081 used bus holder and internal data bus for data transfer with the MPU. When writing data from the
MPU to internal RAM, data is automatically transferred the bus holder to the RAM as shown in figure 4. And when
reading data from internal RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read)
and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5. This means
that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is
executed. Therefore, the data of the specified address cannot be output with the read display data instruction right
after the address sets, but can be output at the second read of data.
Figure 4. Write Timing
MPU signals
RS
WR
D7 ~ D0
N
D(N)
D(N+1)
D(N+2)
D(N+3)
Internal signals
WR
BUS HOLDER
N
D(N)
D(N+1)
D(N+2)
D(N+3)
COLUMN ADDRESS
N
N+1
N+2
N+3
N+4
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