SM5842APT View Datasheet(PDF) - Nippon Precision Circuits
Part Name
Description
MFG CO.
'SM5842APT' PDF : 23 Pages View PDF
SM5842AP/APT
Data Input to Output Delay Timing
This is the digital filter arithmetic computation time from the completion of data input at rate fs (tINPUT) on the
rising edge of LRCI to the start of data output at rate 8fs (tOUTPUT) on the falling edge of WCKO.
Table 7. Output delay
CKSLN
LOW (256fs)
HIGH (384fs)
SYNCN
LOW
HIGH
LOW
HIGH
Mode
After reset + sync mode
Jitter-free mode
After reset + sync mode
Jitter-free mode
tOUTPUT − tINPUT
48.625/fs
48.25/fs − 49.0/fs
48.75/fs
48.375/fs − 49.125/fs
1/fs
LRCI
Serial data Input
tINPUT
48/fs
WCKO
(256fs)
WCKO
(384fs)
tINPUT
tOUTPUT Serial data output
Figure 10. Delay timing 1
tOUTPUT Serial data output
t t OUTPUT− INPUT
Figure 11. Delay timing 2
tOUTPUT
NIPPON PRECISION CIRCUITS—19
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