Software interface
SMCxxxBF
Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd
addresses between 400h and 7FFh access register 9. This 1 KByte memory window to the
data register is provided so that hosts can perform memory-to-memory block moves to the
data register when the register lies in memory space. Some hosts, such as the X86
processors, must increment both the source and destination addresses when executing the
memory-to-memory block move instruction. Some PCMCIA socket adapters also have an
embedded auto incrementing address logic.
A Word access to address at offset 8 will provide even data on the least significant Byte of
the data bus, along with odd data at offset 9 on the most significant Byte of the data bus.
Table 37. Memory Mapped Decoding
–REG A10
A9 to
A4
A3 A2 A1 A0 Offset
–OE=0
–WE=0
10
10
10
10
10
10
10
10
10
X
0 0 0 0 0h Even Data Register
Even Data Register
X
0 0 0 1 1h
Error Register
Feature Register
X
0 0 1 0 2h
Sector Count
Register
Sector Count Register
X
0 0 1 1 3h
Sector Number
Register
Sector Number Register
X
0 1 0 0 4h Cylinder Low Register Cylinder Low Register
X
0 1 0 1 5h
Cylinder High
Register
Cylinder High Register
X
0 1 1 0 6h
Select Card/Head
Register
Select Card/Head
Register
X
0 1 1 1 7h
Status Register
Command Register
X
1 0 0 0 8h
Dup. Even Data
Register
Dup. Even Data Register
10
10
10
10
11
11
X
1 0 0 1 9h
Dup. Odd Data
Register
Dup. Odd Data Register
X
1 1 0 1 Dh Dup. Error Register Dup. Feature Register
X
1 1 1 0 Eh
Alternate Status
Register
Device Control Register
X
1 1 1 1 Fh
Drive Address
Register
Reserved
X
X X X 0 8h Even Data Register
Even Data Register
X X X X 1 9h Odd Data Register
Odd Data Register
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