SMC512BFY6 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
SMC512BFY6
Numonyx -> Micron
'SMC512BFY6' PDF : 91 Pages View PDF
SMCxxxBF
CF-ATA registers
Table 42. Data Register Access (True IDE mode)
Data Register
–CS1
–CS0
PIO Word Data Register
1
0
DMA Word Data Register
1
1
PIO Byte Data Register (Selected Using
Set Features Command)
1
0
A0 -DMACK
0
1
X
0
0
1
Offset
0h
X
0h
Data Bus
D15 to D0
D15 to D0
D7 to D0
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
Error Register
The Error register is a read-only register, located at address 1F1h [171h], offset 1h, 0Dh.
This read only register contains additional information about the source of an error when an
error is indicated in bit 0 of the Status register. The bits are defined in Table 43 This register
is accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and –
CE1 High.
Bit 7 (BBK)
This bit is set when a Bad Block is detected.
Bit 6 (UNC)
This bit is set when an Uncorrectable Error is encountered.
Bit 5
This bit is ‘0’.
Bit 4 (IDNF)
This bit is set if the requested sector ID is in error or cannot be found.
Bit 3
This bit is ‘0’.
Bit 2 (Abort)
This bit is set if the command has been aborted because of a Card status condition (Not
Ready, Write Fault, etc.) or when an invalid command has been issued.
Bit 1
This bit is ‘0’.
Bit 0 (AMNF)
This bit is set when there is a general error.
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