SMH4803A View Datasheet(PDF) - Summit Microelectronics
Part Name
Description
MFG CO.
'SMH4803A' PDF : 19 Pages View PDF
SMH4803A
Preliminary
UV (11)
The UV pin is used as an under-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if UV is less than 2.5V. Program-
mable internal hysteresis is available on the UV input,
adjustable in increments of 62.5mV. Also available is a
filter delay on the UV input.
ENPGB (15)
This is an active high input that controls the PG3# output.
When ENPGB is pulled low the PG3# output is immedi-
ately placed in a high impedance state. When ENPGB is
driven high or left floating then PG3# will be driven low at
a time period of tPGD after PG2# has been active. This pin
has an internal 50kΩ pull-up to 5V.
OV (12)
The OV pin is used as an over-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if OV is greater than 2.5V. A filter
delay is available on the OV input.
5.0VREF & 2.5VREF (13 & 14)
These are precision 5V and 2.5V output reference volt-
ages that may be use to expand the logic input functions
on the SMH4803A. The reference outputs are with re-
spect to VSS.
ENPGA (16)
This is an active high input that controls the PG2# and
PG3# outputs. When ENPGA is pulled low the PG2# and
PG3# outputs are immediately placed in a high impedance
state. When ENPGA is driven high or left floating then
PG2# will be driven low at a time period of tPGD after PG1#
has been active. This pin has an internal 50kΩ pull-up to
5V.
PG1#, PG2#, & PG3# (18, 19, & 17)
The PGn# pins are open-drain, active-low outputs with no
internal pull-up resistor. They can be used to switch a load
or enable a DC/DC converter. PG1# is enabled immedi-
ately after VGATE reaches VDD – VGT and the DRAIN
SENSE voltage is less than 2.5V. Each successive PG
output is enabled tPGD after its predecessor, provided also
that the appropriate ENPG input(s) are high. Voltage on
these pins cannot exceed 12V, as referenced to VSS.
VDD (20)
VDD is the positive supply connection. An internal shunt
regulator limits the voltage on this pin to approximately
12V with respect to VSS. A resistor must be placed in
series with the VDD pin to limit the regulator current (RD in
the application illustrations).
VSS (10)
VSS is connected to the negative side of the supply.
RECOMMENDED OPERATING CONDITIONS
Temperature –40°C to 85°C.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ...................... –55°C to 125°C
Storage Temperature ........................... –65°C to 150°C
Lead Solder Temperature (10s) ........................... 300°C
Terminal Voltage with Respect to VSS:
VGATE ......................................... VDD + 0.5V
UV, OV, CBSENSE, DRAIN SENSE,
FAULT#, PG1#, PG2#,
and PG3# ...................... –0.5V to VDD + 0.5V
PD1#, PD2#, MODE, RESET#,
ENPGA, ENPGB, EN/TS ......................... 10V
*Comment
Stresses listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
2051 4.4 3/15/01
SUMMIT MICROELECTRONICS, Inc.
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