SMH4803A
Preliminary
VDD
UV
OV
11 ≤ VDD ≤ 13
2.5VREF
<tPUVF
PD1#/
PD2#
VGATE
tPDD
VDD – VGT
VDD
DRAIN
SENSE
CBSENSE
PG1#
ENPGA
PG2#
ENPGB
PG3#
5V
50mVREF
2.5VREF
tPGD
<tCBD
tPGD
Figure 1. Complete Power On Timing Sequence
2051 Fig01 1.1
TIMING RELATIONSHIPS
Figure 1 illustrates some of the power on sequences,
including the UV and OV differentials to their reference,
and Power Good cascading.
Figures 2, 3, and 4 indicate the affect on the VGATE
signal caused by different Circuit Breaker inputs. In
Figure 2 RESET# and MODE are high; in Figure 3
MODE is low. Figure 4 shows the Quick Trip mode.
2051 4.4 3/15/01
SUMMIT MICROELECTRONICS, Inc.
8