SPEAR300-2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

SPEAR300-2

Embedded MPU with ARM926 core, flexible memory support, powerful connectivity features and human machine interface

STMicroelectronics 

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SPEAr300

Description

1.1

Main features:

● ARM926EJ-S 32-bit RISC CPU, up to 333 MHz

– 16 Kbytes of instruction cache, 16 Kbytes of data cache

– 3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code

density, bytecode Java mode (Jazelle™) for direct execution of Java code.

– AMBA bus interface

● 32-KByte on-chip BootROM

● 8-KByte on-chip SRAM

● 16-bit mobile DDR/DDR2 memory controller (up to 333 MHz)

● Serial memory interface

● SDIO/MMC interface supporting SPI, SD1, SD4 and SD8 mode with card detect, write

protect, LED

● 8/16-bits NOR Flash/NAND Flash controller

● Boot capability from NAND Flash, serial/parallel NOR Flash, Ethernet and UART

● Boot and field upgrade capability from USB

● Multichannel DMA controller

● Color LCD Controller for STN/TFT display panels

– up to 1024 x 768 resolution

– 24 bpp true color

● Up to 62 GPIOs (muxed with peripheral I/Os), up to 22 with interrupt capability

● JPEG CODEC accelerator, 1 clock/pixel

● Camera interface ITU-601 with external or embedded synchronization (ITU-656 or

CSI2). Picture limit is given by the line length that must be stored in a 2048 x 32 buffer

● C3 Crypto accelerator (DES/3DES/AES/SHA1)

● TDM master/slave

– Up to 512 timeslots

– Any input timeslot can be switched to any output timeslot, and/or can be buffered

for computation

– Up to 16 channels of 1 to 4 timeslots buffered during 32 ms

– Up to 16 buffers can be played in output timeslots

● I2S interface, full duplex with data buffer for left and right channels allowing up to 64 ms

of voice buffer (for 32 bit samples).

● 10-bit ADC, 1 Msps, 8 inputs/1-bit DAC

● 9 x 9 keyboard controller

● Ethernet MAC 10/100 Mbps (MII PHY interface)

● Two USB2.0 host (high-full-low speed) with integrated PHY transceiver

● One USB2.0 device (high-full-low speed) with integrated PHY transceiver

● SSP master/slave (Motorola SPI, Texas instruments, National semiconductor

protocols) up to 50 Mbps

● I2C (slow- fast-high speed, up to 1.2 Mb/s) master/slave

● I/O peripherals

– UART (speed rate up to 3 Mbps)

– IrDA (FIR/MIR/SIR) 9.6 kbps to 4 Mbps speed-rate

Doc ID 16324 Rev 2

9/83

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