SPT5420SIM View Datasheet(PDF) - Signal Processing Technologies
Part Name
Description
MFG CO.
'SPT5420SIM' PDF : 8 Pages View PDF
VOLTAGE REFERENCES AND
ANALOG GROUND INPUTS
Three VREFTXX and three VREFBXX inputs set the output
range of the three corresponding groups of DACs (0 and 1;
2 through 5; 6 and 7). Four RGNDXX inputs set the output
offset voltage of the four corresponding groups of DACs (0
and 1; 2 and 3; 4 and 5; 6 and 7). The formula for output
swing and offset are presented in the “Analog Outputs”
section below.
MULTIPLYING OPERATION
The SPT5420’s references accept AC and DC signals.
Therefore, it can be used for multiplying applications.
VREFTXX should normally have a positive input voltage and
VREFBXX should normally have a negative input voltage.
When applying AC signals to the references, filter these in-
puts instead of bypassing.
DAC ADDRESSING AND LATCHING
Each DAC has an input latch which receives data from the
data bus, and a DAC latch which receives data from the in-
put latch. The analog output of each DAC corresponds to
the data in its DAC latch. One of the eight input latches is
addressed by the address lines A(2:0) according to Table I.
While CS and WR are low, the addressed input latch is
transparent and the seven other input latches are latched.
Bringing CS or WR high latches data into the addressed in-
put latch. While LDAC is low, all eight DAC latches are
transparent. Bringing LDAC high latches data into the DAC
latches. While CS, WR and LDAC are low, both latches are
transparent and input data is transferred directly to the
selected DAC. While CLR is low, all DAC outputs are set to
their corresponding RGNDXX. Bringing CLR high returns
each DAC’s output to the voltage corresponding to the data
in each DAC latch.
Table II summarizes this information and Figures 1a, 1b and
1c should be referenced for timing limitations.
ANALOG OUTPUTS
The output voltage range is equal to twice the difference
between VREFTXX and VREFBXX. The output voltage is given
by:
INPUT CODE
VOUT = 2 X (VREFB +[VREFT – VREFB] X
8192
) – VRGND
Table I – DAC Addressing
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Addressed Input
Latch DAC#
0
1
2
3
4
5
6
7
Table II – Control Logic Table
WR CS LDAC CLR Input Latch DAC Latch
0
0
x
1 transparent1
x
1
x
x
1
latched
x
x
1
x
1
latched
x
x
x
0
1
x
transparent
x
x
1
1
x
latched
x
x
x
0
DAC outputs at RGNDXX
Note 1: Only the input latch addressed by A(2:0) is transparent.
The other input latches are latched.
DIGITAL INPUT CODES
All 0s in a DAC latch produces negative-full-scale output
voltage. All 1s produces positive-full-scale.
POWER SUPPLY SEQUENCING
The sequence in which VDD, VSS and VCC come up is not
critical. The reference inputs – VREFTXX and VREFBXX – must
come on only after VDD and VSS have been established.
However, they may be turned on prior to VCC. The digital
inputs must be driven only after VCC has been established.
Reverse the power-on sequence for power-down.
SPT
4
SPT5420
10/11/00
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