SPT5420SIM View Datasheet(PDF) - Signal Processing Technologies
Part Name
Description
MFG CO.
'SPT5420SIM' PDF : 8 Pages View PDF
Figure 1a – Timing Diagram: Latched Mode
(LDAC Strobed)
t1
t2
A0–A2
CS
WR
D0–D12
t3
t5
t6
t4
t7
t8
t9
VOUT
t10
LDAC
Figure 1c – Timing Diagram: CLR Function
t11
CLR
t9
VOUT
Figure 1b – Timing Diagram: Transparent Mode
(LDAC Held Low)
t1
t2
A0–A2
CS
WR
D0–D12
VOUT
t3
t5
t6
t4
t7
t8
t9
PARAMETER
SYMBOL MIN TYP MAX UNIT
Address Valid to WR Setup
t1
15
ns
Address Valid to WR Hold
t2
0
ns
CS Pulse Width Low
t3
50
ns
WR Pulse Width Low
t4
50
ns
CS to WR Setup
t5
0
ns
WR to CS Hold
t6
0
ns
Data Setup
t7
20
ns
Data Hold
t8
0
ns
Settling Time
t9
20
us
LDAC Pulse Width Low
t10
50
ns
CLR Pulse Activation
t11
300 ns
NOTES:
1. All digital input rise and fall times are measured from 10% to
90% of +5 V. tr = tf = 5 ns.
SPT
5
SPT5420
10/11/00
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