SRTAG2KL
SRTAG2KL memory management
If enabled, the Read/Write counter will have an impact on the execution time of the event
which is countered: the counter increment needs some write cycles of specific EEPROM
cells automatically managed by SRTAG2KL, which increase the total time before the
response is sent to the reader.
As a consequence, an S(WTX) request can be issued on the command that will increment
the counter (see Section 5.4).
DocID026583 Rev 2
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