SST89V554RC-25-C-PI View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
MFG CO.
'SST89V554RC-25-C-PI' PDF : 62 Pages View PDF
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
2 except read operation isn’t available. The fourth level
of security is the most secure level. It doesn’t allow
read/program of internal memory or boot from external
memory. Please note that for unused combinations of
the security lock bits, the chip will default to Level 4
status. For details on how to program the security lock
bits refer to the External Host Mode and In-Application
Programming Section.
UUU/NN
PUU/SS
Level 1
Level 2
UPU/SS
UPP/LL
PPU/LS
UUP/LS
Level 3
PUP/LL
UPP/LL
PPP/LL
Level 4
555 ILL F19.0
FIGURE 9-1: SECURITY LOCK LEVELS
Note: P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1), N = Not Locked, L = Hard Locked, S = SoftLocked
.
TABLE
Level
1
2
9-1: SECURITY LOCK OPTIONS
Security Lock Bits1,2
SFST[7:5] SB1
SB21
000
U
U
100
P
U
SB31
U
U
Security Status of:
Block 1
Block 0
Unlock
Unlock
SoftLock
SoftLock
3
011
U
P
P Hard Lock Hard Lock
101
P
U
P
010
U
P
U SoftLock
SoftLock
110
P
P
U Hard Lock SoftLock
001
U
U
P
4
111
P
P
P Hard Lock Hard Lock
1. P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1).
2. SFST[7:5] = Security Lock Decoding Bits (SECD)
Security Type
No Security Features are Enabled.
MOVC instructions executed from
external program memory are dis-
abled from fetching code bytes from
internal memory, EA# is sampled and
latched on Reset, and further pro-
gramming of the flash is disabled.
Level 2 plus Verify disabled, both
blocks locked.
Level 2 plus Verify disabled. Code in
Block 1 may program Block 0 and vice
versa.
Level 2 plus Verify disabled. Code in
Block 1 may program Block 0.
Same as Level 3 Hard Lock/Hard
Lock, but MCU will start code execu-
tion from the internal memory regard-
less of EA#.
T9-1.0 555
©2001 Silicon Storage Technology, Inc.
45
S71207-00-000 9/01 555
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