SST89V554RC-25-C-PI View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
MFG CO.
'SST89V554RC-25-C-PI' PDF : 62 Pages View PDF
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 10-1: INTERRUPT POLLING SEQUENCE
Description
Ext. Int0
Brown-out
T0
Ext. Int1
T1
UART/SPI
T2
Interrupt Flag
IE0
BOF
TF0
IE1
TF1
TI/RI/SPIF
TF2, EXF2
Vector
Address
0003H
004BH
000BH
0013H
001BH
0023H
002BH
Interrupt
Enable
EX0
EBO
ET0
EX1
ET1
ES
ET2
Interrupt
Priority
PX0/H
PBO/H
PT0/H
PX1/H
PT1/H
PS/H
PT2/H
Arbitration
Ranking
1(highest)
2
3
4
5
6
7
Wake-Up
Power Down
yes
no
no
yes
no
no
no
T10-1.0 555
10.5 Power-Saving Modes
The device provides three power saving modes of opera-
tion for applications where power consumption is critical.
The three power saving modes are: Idle, Power Down and
Standby (Stop Clock).
10.5.1 Idle Mode
Idle mode is entered setting the IDL bit in the PCON regis-
ter. In Idle mode, the program counter (PC) is stopped. The
system clock continues to run and all interrupts and periph-
erals remain active. The on-chip RAM and the special func-
tion registers hold their data during this mode.
The device exits Idle mode through either a system inter-
rupt or a hardware reset. Exiting Idle mode via system
interrupt, the start of the interrupt clears the IDL bit and
exits Idle mode. After exit the Interrupt Service Routine, the
interrupted program resumes execution beginning at the
instruction immediately following the instruction which
invoked the Idle mode. A hardware reset starts the device
similar to a power-on reset.
10.5.2 Power Down Mode
The Power Down mode is entered by setting the PD bit in
the PCON register. In the Power Down mode, the clock is
stopped and external interrupts are active for level sensitive
interrupts only. To retain the on-chip RAM and all of the spe-
cial function registers’ values, the minimum VDD level is 2.0V.
The device exits Power Down mode through either an
enabled external level sensitive interrupt or a hardware
reset. The start of the interrupt clears the PD bit and exits
Power Down. Holding the external interrupt pin low restarts
the oscillator, the signal must hold low at least 1024 clock
cycles before bringing back high to complete the exit. After
exit the interrupt service routine program execution
resumes beginning at the instruction immediately following
the instruction which invoked Power Down mode. A hard-
ware reset starts the device similar to power-on reset.
To exit properly out of Power Down, the reset or external
interrupt should not be executed before the VDD line is
restored to its normal operating voltage. Be sure to hold
VDD voltage long enough at its normal operating level for
the oscillator to restart and stabilize (normally less than
10 ms).
10.5.3 Standby Mode (Stop Clock)
Standby mode is similar to Power Down mode, except that
Power Down mode is initiated by a software command and
Standby mode is initiated by external hardware gating off
the external clock to the device.The on-chip SRAM and
SFR data are maintained in Standby mode. The device
resumes operation at the next instruction when the clock is
reapplied to the part.
Table 10-2 outlines the different power-saving modes,
including entry and exit procedures and MCU functionality.
©2001 Silicon Storage Technology, Inc.
48
S71207-00-000 9/01 555
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