FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
4. Capacitive loading on Ports 0 & 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when
the address bits are stabilizing.
5. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
7. See Figures 11-1, 11-2, 11-3 and 11-4 for test conditions. Minimum VDD for Power Down is 2.0V.
VDD
RST
VDD
VDD
IDD
VDD
P0
EA#
89x564
CLOCK (NC)
SIGNAL
XTAL2
XTAL1
VSS
All other pins disconnected
555 ILL F22.0
FIGURE 11-1: IDD TEST CONDITION,
ACTIVE MODE
CLOCK (NC)
SIGNAL
VDD
VDD
IDD
VDD
P0
RST
EA#
89x564
XTAL2
XTAL1
VSS
All other pins disconnected
555 ILL F23.0
FIGURE 11-2: IDD TEST CONDITION,
IDLE MODE
(NC)
VDD = 2V
VDD
VDD
IDD
VDD
P0
RST
EA#
89x564
XTAL2
XTAL1
VSS
All other pins disconnected
555 ILL F24.0
FIGURE 11-3: IDD TEST CONDITION,
POWER-DOWN MODE
(NC)
VDD = 5V
VDD
VDD
IDD
VDD
P0
RST
EA#
89x564
XTAL2
XTAL1
VSS
All other pins disconnected
555 ILL F25.0
FIGURE 11-4: IDD TEST CONDITION,
STANDBY (STOP CLOCK) MODE
©2001 Silicon Storage Technology, Inc.
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S71207-00-000 9/01 555