ST10F168-Q3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F168-Q3' PDF : 74 Pages View PDF
ST10F168
Hardware traps are exceptions or error conditions
that arise during run-time. They cause immediate
non-maskable system reaction similar to a stan-
dard interrupt service (branching to a dedicated
vector table location).
The occurrence of a hardware trap is
additionally signified by an individual bit in the
trap flag register (TFR). Except when another
higher prioritized trap service is in progress, a
hardware trap will interrupt any other program
execution.
Hardware trap services cannot not be interrupted
by standard interrupt or by PEC interrupts.
Table 10 shows all of the possible exceptions or
error conditions that can arise during run-time :
Table 10 : Exceptions or error conditions that can arise during run-time
Exception Condition
Reset Functions
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps
Undefined Opcode
Protected Instruction Fault
Illegal Word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
Trap Flag Trap Vector
RESET
RESET
RESET
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
Vector Location
00’0000h
00’0000h
00’0000h
00’0008h
00’0010h
00’0018h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
[2Ch –3Ch]
Trap Number Trap Priority
00h
III
00h
III
00h
III
02h
II
04h
II
06h
II
0Ah
I
0Ah
I
0Ah
I
0Ah
I
0Ah
I
[0Bh – 0Fh]
Software Traps
TRAP Instruction
Any [00’0000h– 00’01FCh] Any [00h – 7Fh] Current CPU
in steps of 4h
Priority
25/74
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