ST16C1551 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'ST16C1551' PDF : 37 Pages View PDF
ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
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REV. 4.2.0
FIGURE 14. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED]
Start
Bit
RX
S D0:D7 S D0:D7 T
Stop
Bit
INT
First Byte is
TSSR
Received in
RX FIFO
RXRDY
(ISR bit-5)
IOR#
(Reading data out
of RX FIFO)
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
TSSI
RX FIFO drops
below RX
Trigger Level
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
FIFO
Empties
TRRI
TRR
RXINTDMA#
FIGURE 15. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED]
Start
Bit
Stop
Bit
RX
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
INT
RXRDY
(ISR bit-5)
TSSI
RX FIFO fills up to RX
Trigger Level or RX Data
TSSR
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXFIFODMA
30
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