ST16C552A View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'ST16C552A' PDF : 39 Pages View PDF
ST16C552/552A
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the eighteen 552/552A internal registers. The
assigned bit functions are more fully defined in the following paragraphs.
Table 7, ST16C552/552A INTERNAL REGISTERS
A2 A1 A0
Register
[Default]
Note 5*
BIT-7
BIT-6
General Register Set: Note 1*
0 0 0 RHR [XX]
bit-7
bit-6
000
THR [XX]
bit-7
bit-6
001
IER [00]
0
0
010
010
FCR [00]
ISR [01]
RCVR
trigger
(MSB)
FIFO’s
enabled
RCVR
trigger
(LSB)
FIFO’s
enabled
BIT-5
bit-5
bit-5
En
Pwr
down
mode
0
0
011
LCR [00]
100
MCR [00]
divisor
latch
enable
Pwr
down
set
break
0
set
parity
0
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
bit-4
bit-4
0
0
0
even
parity
loop
back
bit-3
bit-2
bit-1
bit-0
bit-3
bit-2
bit-1
bit-0
Modem
Status
Interrupt
Receive
Line
Status
interrupt
Transmit
Holding
Register
interrupt
Receive
Holding
Register
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
INT
priority
bit-2
INT
priority
bit-1
INT
priority
bit-0
INT
status
parity
stop
word
word
enable
bits
length
length
bit-1
bit-0
INT A/B
[X]
enable
-RTS
-DTR
101
LSR [60]
110
MSR [X0]
FIFO
data
error
CD
THR &
TSR
empty
RI
111
SPR [FF]
bit-7
bit-6
Special Register Set: Note *2
000
DLL [XX]
bit-7
bit-6
001
DLM [XX]
bit-15
bit-14
THR.
empty
break
interrupt
framing
error
DSR
bit-5
CTS
bit-4
delta
-CD
bit-3
bit-5
bit-13
bit-4
bit-12
bit-3
bit-11
parity
error
delta
-RI
bit-2
bit-2
bit-10
overrun
error
delta
-DSR
bit-1
receive
data
ready
delta
-CTS
bit-0
bit-1
bit-0
bit-9
bit-8
Rev. 3.40
16
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