ST16C552A View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'ST16C552A' PDF : 39 Pages View PDF
ST16C552/552A
FCR BIT 4-5:
Not Used - initialized to a logic 0.
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, RX trigger level = 1)
These bits are used to set the trigger level for the
receive FIFO interrupt.
An interrupt is generated when the number of charac-
ters in the FIFO equals the programmed trigger level.
However the FIFO will continue to be loaded until it is
full.
BIT-7
0
0
1
1
BIT-6
0
1
0
1
RX FIFO trigger level
01
04
08
14
Interrupt Status Register (ISR)
The 552/552A provides four levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with
four interrupt status bits. Performing a read cycle on
the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are
acknowledged until the pending interrupt is serviced.
Whenever the interrupt status register is read, the
interrupt status is cleared. However it should be noted
that only the current pending interrupt is cleared by the
read. A lower level interrupt may be seen after reread-
ing the interrupt status bits. The Interrupt Source
Table 8 (below) shows the data values (bits 0-3) for the
four prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels:
Table 8, INTERRUPT SOURCE TABLE
Priority
[ISR BITS]
Level Bit-3 Bit-2 Bit-1 Bit-0 Source of the interrupt
1
0 1 1 0 LSR (Receiver Line Status Register)
2
0 1 0 0 RXRDY (Received Data Ready)
2
1 1 0 0 RXRDY (Receive Data time out)
3
0 0 1 0 TXRDY (Transmitter Holding Register Empty)
4
0 0 0 0 MSR (Modem Status Register)
Rev. 3.40
20
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