ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
ST18-AU1
13.2 Clocks and timers registers
PSCTR register)
15 14 13 12 11 10
9
8
76543210
- - - - - - CLK_sel CLK_sel
2
1
SCLKINTDIV
Bit
SCLKINT-
DIV
CLK_sel1
CLK_sel2
-
Function
SCLKINTDIV prescaler divide factor
00000000
1
00000001
2
...
...
11111111
510
fSCLKINT= fpll2/2(SCLKINTDIV) if SCLKINTDIV /= 00000000
PCM output clock select:
0
Hardware (MCLK_MODE pin)
1
Software (according to bit 9)
PCM Output Clock select:
0
MCLK_PCM= output of prescaler: SCLK is system clock output
1
MCLK_PCM= SCLK: SCLK is system clock input
RESERVED, read as 0.
STC: system time clock registers
• input = EXTAL1 (27 MHz)
• output = STC
A Prescaler divides by 300 the master clock and generates the input clock at 90 KHz for STC.
The 90 KHz clock is synchronized to the D950 instruction clock.
STC is a 32-bit counter incremented at each 90 KHz clock pulse. It can be initialized to any
value and read by the D950. It is memory mapped as two registers, STCMTR and STCLTR.
STCMTR: 16-bit (MSB)
STCLTR: 16 bit (LSB)
Note:
When initializing the STC, the STCLTR register must be written before the STCLMTR. The
effective loading of the STC occurs after STCMTR loading: When reading the STC, the
STCLTR register must be read first. At that time, the current value of the STC MSB is stored
in the STCMTR register, which can then be read.
No interrupts are associated with the STC.
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