ST20-C1 View Datasheet(PDF) - STMicroelectronics
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MFG CO.
'ST20-C1' PDF : 205 Pages View PDF
value MostNeg) at the bottom of the memory space.
Queue control block
Back
Front
Front
Iptr
Wptr
Iptr
Wptr
Iptr
Wptr
7 Multi-tasking
Back
Iptr
Wptr
Process descriptor blocks
Figure 7.4 A process queue
7.4 Timeslicing
The ST20-C1 includes support for timeslicing. Timeslicing is a safeguard in a multi-
tasking environment to prevent any one process from taking too much processor time.
Exception handlers are not timesliced.
A timeslicing counter is provided as a field of the status register called the
timeslice_count. It is reset to MaxTimesliceCount each time a user process is loaded
from the scheduling queue into the CPU. The counter is decremented regularly until it
reaches 0, and then stays at 0. A timeslice is due when the counter value is 0.
If a timeslice instruction is executed when a timeslice is due and timeslicing is enabled
then:
• the timeslice trap will be taken if it is installed;
• otherwise the current process will be timesliced, i.e. the current process is
placed on the back of the scheduling queue and the process on the front of the
scheduling queue is loaded into the CPU for execution.
If an exception occurs, the value of the counter is saved with the status register and
reloaded when the interrupted or trapped process is restarted. This ensures that a
process will be executed for roughly the same time regardless of whether it was inter-
rupted or trapped.
The timeslice_enable bit of the status register can be used to enable or disable
timeslicing. Timeslicing is enabled when the bit is set. This bit is preserved when a
process is descheduled, so it may be treated as global among user processes. Times-
licing must not be enabled in exception handlers.
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