ST20-C1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST20-C1' PDF : 205 Pages View PDF
7 Multi-tasking
7.9.1 Waiting for a resource
A process requesting a resource executes a wait (or P), which is the following code
sequence:
ld semaphore; wait;
cj CONTINUE;
stop;
CONTINUE:
The wait instruction is executed, with a pointer to the semaphore control block in
Areg. The action of wait depends on the count in the semaphore control block. If the
count is not zero, then a resource is free, so the count of free resources is decre-
mented and the value false is left in the Areg to indicate that the process can
continue. If the count is zero then there are no free resources, and the process is
added to the list of waiting processes, and the value true is left in Areg to indicate that
the process must wait. A conditional jump then tests Areg and performs a stop if the
process must wait. stop saves the Iptr and Wptr and deschedules the process, which
will wait on the semaphore queue until another process performs a signal and subse-
quently restarts the process with a run instruction.
7.9.2 Freeing a resource
When a process finishes with a resource and can free it, it performs a signal (or V),
which is the following code sequence:
ld semaphore; signal;
cj CONTINUE;
run;
CONTINUE:
The signal instruction is executed, with a pointer to the semaphore control block in
Areg. The action of signal depends on whether a process is waiting or not. If the front
pointer of the process waiting list is empty then there are no processes waiting, so the
count is incremented and Areg is set to false. Otherwise, at least one process is
waiting, so the first process is remo ved from the list and placed in the Breg, and Areg
is set to true. A conditional jump tests Areg and performs a run to restart the process
if there was one waiting.
7.10 Sleep
When the ST20-C1 becomes idle it disables counter distribution to its circuits and
consumes a very small amount of electrical power; this is known as sleep mode. The
counters are re-enabled and normal operation resumes automatically and instantly
when either an interrupt or a software reset from the diagnostic controller is received.
Sleep mode may also be triggered directly from software by setting the sleep bit in the
status register:
ldc sleep; bitmask; statusset;
In this case also, sleep mode persists until the next interrupt or software reset.
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