ST40RA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA' PDF : 94 Pages View PDF
ST40RA
5 System configuration
5.8.1 Memory bridge control signals
Each memory bridge has seven control signals as defined in Table 10.
Bridge control bit field
1:0
4:2
5
6
Control name Control function
MODE[1:0]
00: Sync (bypass) bridge
01: Semisync with no retime registers
10: Semisync with one retime register
11: Async with two retime registers
LATENCY[2:0]
SW_RESET
STROBE
Sets FIFO latency from 0 to 7 cycles.
0: Software reset inactive
1: Software reset active
The above control signals are latched in the bridge on the rising
edge of this strobe bit
Table 10: Memory bridge control signals
5.8.2
Memory bridge status
The memory bridge control signals are looped back to the ST40RA comms subsystem SYS_STAT1
register for test purposes. The format of this read-only register is shown in Section 5.9.4.1:
SYSCONF.SYS_STAT1. on page 26.
5.8.3
Changing control of a memory bridge
At reset all these bridges are set to be synchronous. After reset and boot the function of these
memory bridges can be changed. See Section 5.9.4: SYSCONF registers on page 26. The
procedure for changing the control of a memory bridge is given below.
1 Ensure no initiators are accessing the subsystem the bridge is connected to and ensure the
subsystem cannot initiate any requests to the SuperHyway.
2 Stop the clock to the subsystem.
3 Change the memory bridge configuration using the SYS_CONF.SYS_CON1 register as
detailed in Table 10.
4 Restart the clock to the subsystem and reinitialize the system.
ADCS 7260755H
STMicroelectronics 22/94
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