5 System configuration
ST40RA
5.9 System configuration registers
Table 11 outlines the ST40RA system configuration registers.
Register
Module
Address
offset
Type
Description
EMI.GENCFG
EMI
0x028
LMI.COC
LMI.CIC
SYS_STAT1
SYSCONF.SYS_CON1
LMI
0x028
LMI
0x040
SYSCONF 0x040
SYSCONF 0x010
SYSCONF.SYS_CON2
SYSCONF 0x018
SYSCONF.CNV_STATUS SYSCONF 0x020
SYSCONF.CNV_SET
SYSCONF 0x028
SYSCONF.CNV_CLEAR
SYSCONF 0x030
SYSCONF.CNV_CONTROL SYSCONF 0x038
R/W
R/W
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
EMI general purpose configuration register, see
Section 5.9.1: EMI.GENCFG EMI general
configuration on page 24
LMI clock and pad control register, see
Section 5.9.2: LMI.COC on page 25
LMI clock and pad status, see Section 5.9.3:
LMI.CIC on page 26
Memory bridge status, see Section 5.9.4.1:
SYSCONF.SYS_STAT1. on page 26
System configuration register, see
Section 5.9.4.2: SYSCONF.SYS_CON1. on
page 27
System configuration register, see Section 5.9.5:
SYSCONF.SYS_CON2. on page 27
System configuration register, see ST40 System
Architecture Manual Volume 4: I/O Devices
System configuration register, see ST40 System
Architecture Manual Volume 4: I/O Devices
System configuration register, see ST40 System
Architecture Manual Volume 4: I/O Devices
System configuration register, see ST40 System
Architecture Manual Volume 4: I/O Devices
Table 11: System configuration registers
23/94 STMicroelectronics
ADCS 7260755H