ST40RA View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST40RA

32-bit Embedded SuperH Device

STMicroelectronics 

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ST40RA

6 Clock generation

6.6.6 CLOCKGENA.STBACKCR and CLOCKGENB.STBACKCR register

CLOCKGENA.STBACKCR

CLOCKGENB.STBACKCR

Current module power status

This register indicates the current module power status

[0:7] ACK[0:7]

Power down status for module [n]

Indicates the current power down status of the

module [n]

Bit [n]: 0 Module [n] operating normally

Bit [n]: 1 Module [n] powered down

Reset state: 0

[8:31] Reserved

0: No action

1: Undefined

Reset state: Undefined

0x0030

RO

Table 19 defines the mapping of modules to bits in the STBREQ and STBACK registers.

Bit number

CLOCKGENA

mapping

CLOCKGENB

mapping

0

EMI

Reserved

1

LMI

Reserved

2

DMAC

Reserved

3

PCI

Reserved

4

PIO

Reserved

5

Reserved

Reserved

6

Reserved

PCI bus

7

Reserved

Reserved

Table 19: STBREQ and STBACK mapping for modules

ADCS 7260755H

STMicroelectronics 42/94

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