7 Electrical specifications
7.4 LMI interface (SDRAM) AC specifications
LCLKOUTA
LCLKOUTB
Outputs
Tri-state outputs
Inputs
tLCHLCH
tLCHLCL
tLCLLCH
tLCLLOV
tLCHLON
tLCHLOZ
tLCHLIX
tLIVLCH
ST40RA
Figure 11: LMI SDRAM mode timings
Symbol
tLCHLCH
tLCHLCL
tLCLLCH
tLCHLOV
tLCHLOZ
tLCHLON
tLIVLCH
tLCHLIX
Parameter
Min
LMI clock period
10
LMI clock high time
0.45
LMI clock low period
0.45
LCLKOUT low to output signals valid
-2
LCLKOUT high to outputs tri-state
0
LCLKOUT high to outputs on
-2
Input signals valid to LCLKOUT high
2
Input signals hold after LCLKOUT high
2
Table 26: LMI SDRAM AC timings
Max
2
2
Units
ns
tLCHLCH
tLCHLCH
ns
ns
ns
ns
ns
Note
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ADCS 7260755H