ST40RA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA' PDF : 94 Pages View PDF
8 Pin description
8 Pin description
ST40RA
8.1 Function pin use selection
Full details of the functional pin sharing are found in Section 8.3: PBGA 27 x 27 ballout on page 61.
Functional pin
group
Pins
Alternate use(s)
High-end interactive
set-top box (with STi5514)
example use
PCI request and
grant
PCI request and
grant
NOTPREQ[0:3]
NOTPGNT[0:3]
NOTPINTA
NOTPREQ[2:3]
NOTPGNT[2:3]
GPDMA
handshake
DACK[0:1]
DREQ[0:1]
DRAQ[0:1]
2 x SCIF
SCI2, CTS1
RXD0, RXD1
SCK0, SCK1
TXD0, TXD1
PIO[14:23]
PIO[14:23]
EMPIDREQ[0:1]
EMPIDACK[0:1]
PIO[8:13]
EMPIDREQ[2:3]
EMPIDACK[2:3]
EMPIDRACK[2:3]
PIO[0:7]
PCI bus
PCI bus
GPDMA
2 x SCIF
Table 33: ST40RA functional pin sharing summary
8.2 Mode selection
During the power-on reset cycle a range of basic system configurations can be set up with resistive
pull-ups or pull-downs. A detailed description of these selections is found in the relevant chapters of
the ST40 System Architecture Manual.
See Section 8.3: PBGA 27 x 27 ballout on page 61 for information on which pins these mode inputs
have been placed on the ST40RA.
Mode
pin
Pin name
MODE2:0
MODE4:3
MODE5
EADDR2
EADDR3
EADDR4
EADDR5
EADDR6
EADDR7
Architectur
e signal
name
Block
affected
Description
MD2:0
CLOCKGEN Set system clock operating mode
MD4:3
CLOCKGEN Set PCI clock operating mode
MD5
CLOCKGEN Set clock input source
H: Crystal, L: External
Table 34: Mode selection pins for ST40RA
Notes
a
1
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ADCS 7260755H
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