ST40RA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA' PDF : 94 Pages View PDF
ST40RA
8 Pin description
Mode
pin
Pin name
MODE6
MODE7
MODE8
EADDR8
EADDR9
EADDR10
MODE9 EADDR11
MODE11:
10
EADDR12
EADDR13
MODE12
MODE13
EADDR14
EADDR15
Architectur
e signal
name
Block
affected
Description
MD6
MD7
MD8
MD9
MD11:10
MD12
CLOCKGEN Set enable CKIO
EMISS
Enable MPX arbiter
System
Set endianness
H: Little
L: Big
EMI
Set EMI port
H: Master
L: Slave
EMI
Set booting ROM bus size
00: Reserved
01: 32-bit
10: 16-bit
11: 8-bit
EMI
Enable NOP when accessing flash
MD13
Reserved
Tie high
Notes
b
c
d
MODE14 EADDR16
MD14
PCI
PCI bridge mode
H: Host
L: Satellite
MODE15 EADDR17
MD15
PCI
Reserved: PCI select clock
e
H: External
L: Internal
MODE16 EADDR18
MD16
-
Reserved: Tie high
f
MODE17 EADDR19
MD17
-
MODE18 EADDR20
MD18
-
MODE19 EADDR21
MD19
-
Table 34: Mode selection pins for ST40RA
a. See CLOCKGEN chapter of the ST40 System Architecture Manual for details.
b. ST40RA is always the clock master, providing EMI clocks to the system.
c. See EMI chapter of the ST40 System Architecture Manual for details.
d. reserved for enable retiming stage on EMI padlogic
e. PCI clock is selected externally on the board for ST40RA. The mode pin may be used for clock
selection in future variants.
f. These mode pins are not used in current variants, however, they may be used to enable additional
functionality in future variants
ADCS 7260755H
STMicroelectronics 60/94
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