ST40RA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA' PDF : 94 Pages View PDF
8 Pin description
ST40RA
Pin name
TMUCLK
LPCLKIN
LPCLKOSC
VDDRTC
CLKIN
CLKOSC
AUXCLKOUT
STATUS0
STATUS1
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDSYNC
AUDCLK
NOTASEBRK
DCLK
TCK
TMS
NOTTRST
TDI
TDO
EADDR2
EADDR3
EADDR4
EADDR5
EADDR6
EADDR7
EADDR8
EADDR9
EADDR10
EADDR11
Loc
Architecture
signal name
Pin function
Default
Alternate
E15 TCLK
E12 EXTAL2
E13 XTAL2
E11 VCCRTC
E20 CLKIN
D20 CLKOSC
E19 CKIO
C14 STATUS0
D14 STATUS1
C18 AUDATA0
C17 AUDATA1
C16 AUDATA2
C15 AUDATA3
D15 AUDSYNC
D19 AUDCK
E9 NOTASEBRK/
BRKACK
D11 DCK
D12 TCK
D10 TMS
E7 TRST
E6 TDI
E8 TDO
V4 MA2
U4 MA3
V5 MA4
U5 MA5
U6 MA6
T6 MA7
U7 MA8
T7 MA9
U8 MA10
T8
MA11
RTC output clock
TMU input clock
RTC crystal resonator input: on VDDRTC supply
RTC crystal resonator output: on VDDRTC supply
Real-time clock supply
System clock input: on VDDCORE supply
Crystal resonator pin: on VDDCORE supply
Reference 27 MHz clock
output
Processor operating status
Processor operating status
AUD bus command and data
AUD bus command and data
AUD bus command and data
AUD bus command and data
AUD command valid
AUD clock output
Dedicated emulator pin
Clock for udi
Test clock
Test mode
Test reset
Test data input
Test data output
EMI external address
EMI external address
EMI external address
EMI external address
EMI external address
EMI external address
EMI external address
EMI external address
EMI external address
EMI external address
MODE0
MODE1
MODE2
MODE3
MODE4
MODE5
MODE6
MODE7
MODE8
MODE9
Table 35: PBGA ballout for ST40RA
Pin
Type
Dir
C2B I/O I/O
-
I
-
O
I
-
I
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
C4
I/O
-
I
-
I
-
I
-
I
-
I
-
O
E4
O
I
E4
O
I
E4
O
I
E4
O
I
E4
O
I
E4
O
I
E4
O
I
E4
O
I
E4
O
I
E4
OI
67/94 STMicroelectronics
ADCS 7260755H
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