ST486SMM View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST486SMM' PDF : 34 Pages View PDF
ST486DX - SMM IMPLEMENTATION
The portions of the Configuration Control Registers (CCR1, CCR2, and CCR3) which apply to
SMM and power management are described in the following pages.
Table 2 - 1 CCR1 Register
Register INDEX = C1h
7
6
5
4
3
2
1
0
NO-LOCK MMAC SMAC
SMI
RPL
Reserved
SMI
Enable SMM Pins
SMI = 0:
SMI# input pin is ignored and SMADS# output pin floats. Execution of
SGS Thomson specific SMM instructions will generate an invalid opcode exception.
SMI = 1:
SMI# input/output pin and SMADS# output pin are enabled. SMI must be set
to 1 before any attempted access to SMM memory is made.
SMAC System Management Memory Access
SMAC = 0:
All memory accesses in normal mode go to system memory with ADS# output
active. In normal mode, execution of SGS Thomson specific SMM instructions
generate an invalid opcode exception.
SMAC = 1:
Memory accesses while in normal mode that fall within the specified SMM
address region generate an SMADS# output and access SMM memory. SMI#
input is ignored.
MMAC Main Memory Access
MMAC = 0:
All Memory accesses while in SMM mode go to SMM memory with SMADS#
output active.
MMAC = 1:
Data accesses while in SMM mode that fall within the specified SMM address
region will generate an ADS# output and access main memory. Code fetches
are not effected by the MMAC bit. Code fetches from the SMM address region
always generate an SMADS# output and access SMM memory. If both the
SMAC and MMAC bits are set to 1, the MMAC bit has precedence.
15
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