ST6285B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6285B' PDF : 78 Pages View PDF
ST62T85B/E85B
CPU REGISTERS (Cont’d)
However, if the program space contains more than automatically selected after the reset of the MCU,
4096 bytes, the additional memory in program the ST6 core uses at first the NMI flags.
space can be addressed by using the Program
Bank Switch register.
Stack. The ST6 CPU includes a true LIFO hard-
ware stack which eliminates the need for a stack
The PC value is incremented after reading the ad- pointer. The stack consists of six separate 12-bit
dress of the current instruction. To execute relative RAM locations that do not belong to the data
jumps, the PC and the offset are shifted through space RAM area. When a subroutine call (or inter-
the ALU, where they are added; the result is then rupt request) occurs, the contents of each level are
shifted back into the PC. The program counter can shifted into the next higher level, while the content
be changed in the following ways:
of the PC is shifted into the first level (the original
- JP (Jump) instructionPC=Jump address
- CALL instructionPC= Call address
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
- Relative Branch Instruction.PC= PC +/- offset
into the PC and the value of each level is popped
- Interrupt PC=Interrupt vector
back into the previous level. Since the accumula-
tor, in common with all other data space registers,
- Reset
PC= Reset vector
) - RET & RETI instructionsPC= Pop (stack)
t(s - Normal instructionPC= PC + 1
c Flags (C, Z). The ST6 CPU includes three pairs of
u flags (Carry and Zero), each pair being associated
d with one of the three normal modes of operation:
ro Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
P flag and a ZERO flag. One pair (CN, ZN) is used
te during Normal operation, another pair is used dur-
le ing Interrupt mode (CI, ZI), and a third pair is used
o in the Non Maskable Interrupt mode (CNMI, ZN-
s MI).
b The ST6 CPU uses the pair of flags associated
O with the current mode: as soon as an interrupt (or
- a Non Maskable Interrupt) is generated, the ST6
) CPU uses the Interrupt flags (resp. the NMI flags)
t(s instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
c flags is restored. It should be noted that each flag
du set can only be addressed in its own context (Non
ro Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
P switching and thus retain their status.
te The Carry flag is set when a carry or a borrow oc-
le curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
so the bit tested in a bit test instruction; it also partici-
bpates in the rotate left instruction.
OThe Zero flag is set if the result of the last arithme-
is not stored in this stack, management of these
registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position
if more than 6 nested calls or interrupts are execut-
ed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.
lFigure 7. ST6 CPU Programming Mode
INDEX
b7 X REG. POINTER b0
REGISTER
b7 Y REG. POINTER b0
SHORT
DIRECT
ADDRESSING
b7
V REGISTER
b0
MODE
b7 W REGISTER
b0
b7 ACCUM ULATOR b0
b11
PROGRAM COUNTER
b0
SIX LEVELS
STACK REGISTER
NORMAL FLAGS
INTERRUPT FLAGS
CZ
CZ
tic or logical operation was equal to zero; other-
wise it is cleared.
NMI FLAGS
CZ
Switching between the three sets of flags is per-
formed automatically when an NMI, an interrupt or
VA000423
a RETI instructions occurs. As the NMI mode is
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