ST6285B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6285B' PDF : 78 Pages View PDF
ST62T85B/E85B
4.2 TIMER
The MCU features an on-chip Timer peripheral, The prescaler input can be the internal frequency
consisting of an 8-bit counter with a 7-bit program-
mable prescaler, giving a maximum count of 215.
fINT divided by 12 or an external clock applied to
the TIMER pin. The prescaler decrements on the
The peripheral may be configured in three different rising edge. Depending on the division factor pro-
operating modes.
grammed by PS2, PS1 and PS0 bits in the TSCR.
Figure 20 shows the Timer Block Diagram. The The clock input of the timer/counter register is mul-
external TIMER pin is available to the user. The tiplexed to different sources. For division factor 1,
content of the 8-bit counter can be read/written in the clock input of the prescaler is also that of tim-
the Timer/Counter register, TCR, while the state of er/counter; for factor 2, bit 0 of the prescaler regis-
the 7-bit prescaler can be read in the PSC register. ter is connected to the clock input of TCR. This bit
The control logic device is managed in the TSCR changes its state at half the frequency of the pres-
register as described in the following paragraphs. caler input clock. For factor 4, bit 1 of the PSC is
connected to the clock input of TCR, and so forth.
The 8-bit counter is decremented by the output The prescaler initialize bit, PSI, in the TSCR regis-
(rising edge) coming from the 7-bit prescaler and ter must be set to “1” to allow the prescaler (and
can be loaded and read under program control. hence the counter) to start. If it is cleared to “0”, all
When it decrements to zero then the TMZ (Timer
Zero) bit in the TSCR is set to “1”. If the ETI (Ena-
) ble Timer Interrupt) bit in the TSCR is also set to
t(s “1”, an interrupt request is generated as described
c in the Interrupt Chapter. The Timer interrupt can
u be used to exit the MCU from WAIT mode.
Prod Figure 20. Timer Block Diagram
the prescaler bits are set to “1” and the counter is
inhibited from counting. The prescaler can be
loaded with any value between 0 and 7Fh, if bit
PSI is set to “1”. The prescaler tap is selected by
means of the PS2/PS1/PS0 bits in the control reg-
ister.
Figure 21 illustrates the Timer’s working principle.
olete 8
bs 6
5
O 4
- PSC
3
2
) 1
t(s 0
SELECT
1 OF 7
DATABUS 8
8
8-BIT
COUNTER
3
8
b7 b6 b5
b4
b3
b2
STATUS/CONTROL
REGISTER
TMZ ETI TOUT DOUT PSI PS2
b1
b0
PS1 PS0
Obsolete Produc TIMER
fOSC
SYNCHRONIZATION
LOGIC
:12
LATCH
INTERRUPT
LINE
VA00009
40/78
40
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