ST62E18C View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST62E18C
STMicroelectronics
'ST62E18C' PDF : 74 Pages View PDF
ST62T18C/E18C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
7
0
- LES ESB GEN -
-
-
-
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Bit 7, Bits 3-0 = Unused.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Interrupt sources available on the ST62E18C/
T18C are summarized in the Table 10 with associ-
ated mask bit to enable/disable the interrupt re-
quest.
Table 10. Interrupt Requests and Mask Bits
Peripheral
Register
GENERAL
IOR
TIM ER
TSCR1
A/D CONVERTER ADCR
UART
UARTCR
ARTIME R
SPI
Port PAn
Port PBn
Port PDn
ARMC
SIDR
ORPA-DRPA
ORPB-DRPB
ORPD-DRPD
Address
Register
C8h
D4h
D1h
D7h
E5h
DCh
C0h-C4h
C1h-C5h
C3h-C7h
Mask bit
GEN
ETI
EAI
RXIEN
TXIE N
OVIE
CPIE
EIE
ALL
ORPAn-DRPAn
ORPBn-DRPBn
ORPDn-DRPDn
Masked Interrupt Source
All Interrupts, excluding NMI
TMZ: TIMER Overflow
EOC: End of Conversion
RXRDY: Byte received
TXMT: Byte sent
OVF: ARTIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
End of Transmission
PAn pin
PBn pin
PDn pin
In terrupt
source
All
source 4
source 4
source 4
source 3
source 1
source 1
source 2
source 2
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