ST62E18C View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST62E18C
STMicroelectronics
'ST62E18C' PDF : 74 Pages View PDF
ST62T18C/E18C
4.5 U. A. R. T. (Universal Asynchronous Receiver/Transmitter)
The UART provides the basic hardware for asyn-
chronous serial communication which, combined
with an appropriate software routine, gives a serial
interface providing communication with common
baud rates (up to 76,800 Baud with an 8MHz ex-
ternal oscillator) and flexible character formats.
Operating in Half-Duplex mode only, the UART
uses a 10-bit frame or a 11-bit frame according to
the choosen MCU option. Automatic parity bit gen-
eration is software selectable in the 10-bit charac-
ter format allowing either 7 data bit + 1 parity bit, or
8 data bit transmission. Transmitted data is sent di-
rectly, while received data is buffered allowing fur-
ther data characters to be received while the data
is being read out of the receive buffer register. Data
transmit has priority over data being received.
The UART is supplied with an MCU internal clock
that isalso available in WAIT mode of the processor.
4.5.1 Ports Interfacing
RXD reception line and TXD emission line are
sharing the same external pins as two I/O lines.
Therefore, UART configuration requires to set
these two I/O lines through the relevant ports reg-
isters. The I/O line common with RXD line must be
defined as input mode (with or without pull-up)
while the I/O line common with TXD line must be
defined as output mode (Push-pull or open drain).
In the 11-bit character format option, the transmit-
ted data is inverted and can therefore use a single
transistor buffering stage. Defined as input, the
RXD line can be read at any time as an I/O line
during the UART operation. The TXD pin follows I/
O port registers value when UARTOE bit is
cleared, which means when no serial transmission
is in progress. As a consequence, a permanent
high level has to be written onto the I/O port in or-
der to achieve a proper stop condition on the TXD
line when no transmission is active.
Figure 30. UART Block Diagram
WRIT E
READ
START
DETECTOR
UAR TOE
TXD
DIN DATA SHIFT DOUT
REGISTER
DR
D8 D7 D6 D5 D4 D3 D2 D1 D0
RECEIV E BUFFER
REGISTER
1
MUX
0
RXD1
TXD1
RX and TX
INTE RRUPTS
CONTROL REGIST ER D8
BAUD RATE
fOSC
BAUD RATE x 8
P ROGRAM MABLE
DIVIDE R
VR02009
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