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ST62E18C View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST62E18C' PDF : 74 Pages View PDF
ST62T18C/E18C
5.3 INSTRUCTION SET
The ST6 core offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipulation. The following par-
agraphs describe the different types.
All the instructions belonging to a given type are
presented in individual tables.
Table 20. Load & Store Instructions
Instruction
LD A, X
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
LD V, A
LD W, A
LD A, rr
LD rr, A
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Addressing Mode
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
Indirect
Indirect
Immediate
Immediate
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
. Affected
* . Not Affected
Load & Store. These instructions use one, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
immediate data.
Bytes
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
3
Cycles
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Fl ags
Z
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
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