ST6369 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6369' PDF : 71 Pages View PDF
ST6369
ST6369 CORE
The Core of the ST6369 is implemented inde-
pendently from the I/O or memory configuration.
Consequently, it can be treated as an independent
centralprocessor communicating with I/O and mem-
ory via internal addresses, data, and control busses.
The in-core communication is arranged as shown
in the following block diagram figure; the controller
being externally linked to both the reset and the os-
cillator, while the core is linked to the dedicated on-
chip macrocells peripherals via the serial data bus
and indirectly for interrupt purposes through the
control registers.
Registers
The ST6369 Core has five registers and three
pairs of flags available to the programmer. They
are shown in Figure 4 and are explained in the fol-
lowing paragraphs together with the program and
data memory page registers.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator is addressed in the data
space as RAM location at the FFH address.
Accordingly, the ST6369 instruction set can use
the accumulator as any other register of the data
space.
Figure 4. Core Programming Model
INDEX
REGISTER
b7 X REG. POINTER b0
SHORT
b7 Y REG. POINTER b0 DIRECT
AD DRESSING
b7
V REGISTER
b0
MODE
b7 W REGISTER
b0
b7 ACCUMULATOR b0
b11
PROGRAM COUNTER
b0
SIX LEVELS
STACK REGISTER
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
CZ
CZ
CZ
VA0 004 23
Figure 3. Core Block Diagram
6/67
®
Share Link: 
