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ST6391 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST6391' PDF : 68 Pages View PDF
ST6391,92,93,95,97,99
RESET
The ST639x devices can be reset in two ways: by the
external reset input (RESET) tied low and by the
hardware activated digital watchdog peripheral.
RESET Input
The external active low reset pin is used to reset the
ST638x devices and provide an orderly software
startup procedure. The activation of the Reset pin
may occur at any time in the RUN or WAIT mode.
Even short pulses at the reset pin will be accepted
since the reset signal is latched internally and is only
cleared after 2048 clocks at the oscillator pin. The
clocks from the oscillator pin to the reset circuitry are
buffered by a schmitt trigger so that an oscillator in
start-up conditions will not give spurious clocks.
When the reset pin is held low, the external crystal os-
cillator is also disabled in order to reduce current con-
sumption. The MCU is configured in the Reset mode
as long as the signal of the RESET pin is low. The
processingof theprogramis stoppedandthe standard
Input/Outputports (port A, port B and port C) are in the
input state. As soon as the level on the reset pin be-
comes high, the initialization sequence is executed.
Refer to the MCU initialization sequencefor additional
information.
Watchdog Reset
The ST639x devices are provided with an on-chip
hardware activated digital watchdog function in or-
der to provide a graceful recovery from a software
upset. If the watchdog register is not refreshed and
the end-of-count is reached, then the reset state
will be latched into the MCU and an internal circuit
pulls down the reset pin. This also resets the
watchdog which subsequently turns off the pull-
down and activates the pull-up device at the reset
pin. This causes the positive transition at the reset
pin. The MCU will then exit the reset state after
2048 clocks on the oscillator pin.
Application Notes
An external resistor between VDD and the reset pin
is not required because an internal pull-up device
is provided. The user may prefer to add an external
pull-up resistor.
An internal Power-on device does not guarantee
that the MCU will exit the reset state when VDD is
above 4.5V and therefore the RESET pin should
be externally controlled.
Figure 22. Internal Reset Circuit
RESET
(ACTIVE LOW)
O SCIL LATO R
SIG NAL
1.0k
VDD
300k
TO ST6
RESET
COUNTER
ST6
INTERNAL RESET
WATCHDOG RESET
V A 000 2 0 0
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