ST6391 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6391' PDF : 68 Pages View PDF
ST6391,92,93,95,97,99
RESET (Continued)
Figure 23. Reset & Interrupt Processing
Flow-Chart
RESET
NMI MASK SET
INT LATCH CLEARED
( IF PRESENT )
SELECT
NMI MODE FLAGS
PUT FFEh
ON ADDRESS BUS
YES
IS RESET
STILL PRESENT ?
NO
LOAD PC
FROM RESET LOCATIONS
FFE / FFF
FETCH INSTRUCTION
VA000427
Figure 24. Restart Initialization Program
Flow-Chart
RESET VECTOR
RESET
JP
JP: 2 BYTES/4 CYCLES
INITIALIZATION
ROUTINE
RETI
RETI: 1BYTES/2 CYCLES
VA 000181
MCU Initialization Sequence
When a reset occurs the stack is reset to program
counter, the PC is loaded with the address of the
reset vector (located in the program ROM at ad-
dresses FFEh & FFFh). A jump instruction to the
beginning of the program has to be written into
these locations. After a reset the interrupt mask is
automatically activated so that the Core is in non-
maskable interrupt mode to prevent false or ghost
interrupts during the restart phase. Therefore the
restart routine should be terminated by a RETI in-
struction to switch to normal mode and enable in-
terrupts. If no pending interrupt is present at the
end of the reset routine, the ST639x will continue
with the instruction after the RETI; otherwise the
pending interrupt will be serviced.
RESET Low Power Mode
(ST6392 and ST6399 only)
When the reset pin is low, the quartz oscillator is
Disabled allowing reduced current consumption.
When the reset pin is raised the quartz oscillator is
enabled and oscillations will start to build up.The
internal reset circuitry will count 2048 clocks on the
oscillator pin before allowing the MCU to go out of
the reset state; the clocks are after a schmitt trigger
so that false or multiple counts are not possible.
22/64
®
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