ST72124J View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72124J
STMicroelectronics
'ST72124J' PDF : 153 Pages View PDF
ST72334J/N, ST72314J/N, ST72124J
5.2 POWER SAVING MODES
5.2.1 Introduction
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (fCPU).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscil-
lator status.
Figure 27. Power saving mode consumption / transitions
HALT
Low
ACTIVE-HALT SLOW WAIT
POWER CONSUMPTION
WAI T
SLOW
RUN
High
5.2.2 HALT Modes
The HALT modes are the lowest power consump-
tion modes of the MCU. They are entered by exe-
cuting the ST7 HALT instruction (see Figure 29).
Two different HALT modes can be distinguished:
– HALT: main oscillator is turned off,
– ACTIVE-HALT: only main oscillator is running.
The decision to enter either in HALT or ACTIVE-
HALT mode is given by the main oscillator enable
interrupt flag (OIE bit in CROSS-MCCSR register:
see Table 7).
When entering HALT modes, the I bit in the CC
register is forced to 0 to enable interrupts.
The MCU can exit HALT or ACTIVE-HALT modes
on reception of an interrupt with Exit from Halt
Mode capability or a reset (see Table 6 page 37).
A 4096 CPU clock cycles delay is performed be-
fore the CPU operation resumes (see Figure 28).
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up.
Table 7. HALT Modes selection
MCCSR
OIE
flag
Power Saving Mode entered when HALT
instruction is executed
0 HALT (reset if watchdog enabled)
1 ACTIVE-HALT (no reset if watchdog enabled)
Figure 28. HALT /ACTIVE-HALT Modes timing overview
RUN
HALT OR ACTIVE-HALT
4096 CPU CYCLE
DELAY
RUN
HALT
INS TRUCTIO N
RESET
OR
INTERRUPT
FETCH
VECTO R
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