ST72124J View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72124J

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

STMicroelectronics 

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ST72334J/N, ST72314J/N, ST72124J

POWER SAVING MODES (Cont’d)

5.2.4 SLOW Mode

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (fCPU) to

the available supply voltage.

SLOW mode is controlled by three bits in the

MISCR1 register: the SMS bit which enables or

disables Slow mode and two CPx bits which select

the internal slow frequency (fCPU).

In this mode, the oscillator frequency can be divid-

ed by 4, 8, 16 or 32 instead of 2 in normal operat-

ing mode. The CPU and peripherals are clocked at

this lower frequency.

Note: SLOW-WAIT mode is activated when enter-

ring the WAIT mode while the device is already in

SLOW mode.

Figure 31. SLOW Mode: timing diagram for internal CPU clock transitions

NEW FREQUENCY

ACTIV E WHEN

OSC/4 & OSC/8 = 0

NORMAL MODE ACTIVE

(OSC/4, OSC/8 STOPPED)

fOSC/4

fOSC/8

fCPU

CP1:0

00

01

SMS

NEW FREQUENCY

REQ UEST

10

NORMAL MODE

REQUEST

MISCR1

REGISTE R

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