ST72311
RESET (Cont’d)
3.2.4 Low Voltage Detector Reset
The on-chip Low Voltage Detector (LVD) gener-
ates a static reset when the supply voltage is be-
low a reference value. The LVD functions both
during power-on as well as when the power supply
drops (brown-out). The reference value for a volt-
age drop is lower than the reference value for pow-
er-on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
VLVDUP when VDD is rising
VLVDDOWN when VDD is falling
Provided the minimun VDD value (guaranteed for
the oscillator frequency) is above VLVDDOWN , the
MCU can only be in two modes:
- under full software control or
- in static safe reset
In this condition, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Figure 13. Low Voltage Detector Reset Function
VDD
LOW VOLTAGE
DETECTOR RESET
FROM
WATCHDOG
RESET
RESET
Figure 14. Low Voltage Detector Reset Signal
VLVDUP
VDD
RESET
VLVDDOWN
Note: See electrical characteristics for values of
VLVDUP and VLVDDOWN
Figure 15. Temporization timing diagram after an internal Reset
VDD
VLVDUP
Addresses
Temporization (4096 CPU clock cycles)
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