ST72331N4 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72331N4
8-BIT MCU WITH 8 TO 16K OTP/EPROM, 256 EEPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
STMicroelectronics
'ST72331N4' PDF : 107 Pages View PDF
ST72E331 ST72T331
4.5 MISCELLANEOUS REGISTER
The Miscellaneous register allows to select the
SLOW operating mode, the polarity of external in-
terrupt requests and to output the internal clock.
Register Address: 0020h — Read /Write
Reset Value: 0000 0000 (00h)
7
0
PEI3 PEI2 MCO PEI1 PEI0 PSM1 PSM0 SMS
Bit 7:6 = PEI[3:2] External Interrupt EI3 and EI2
Polarity Options.
These bits are set and cleared by software. They
determine which event on EI2 and EI3 causes the
external interrupt according to Table 7.
Table 7. EI2 and EI3 External Interrupt Polarity
Options
MODE
Falling edge and low level
(Reset state)
Falling edge only
Rising edge only
Rising and falling edge
PEI3 PEI2
0
0
1
0
0
1
1
1
Note: Any modification of one of these two bits re-
sets the interrupt request related to this interrupt
vector.
Bit 5 = MCO Main Clock Out
This bit is set and cleared by software. When set, it
enables the output of the Internal Clock on the
PPF0 I/O port.
0 - PF0 is a general purpose I/O port.
1 - MCO alternate function (fCPU is output on PF0
pin).
Bit 4:3 = PEI[1:0] External Interrupt EI1 and EI0
Polarity Options.
These bits are set and cleared by software. They
determine which event on EI0 and EI1 causes the
external interrupt according to Table 8.
Table 8. EI0 and EI1 External Interrupt Polarity
Options
MODE
Falling edge and low level
(Reset state)
Falling edge only
Rising edge only
Rising and falling edge
PEI1
0
1
0
1
PEI0
0
0
1
1
Note: Any modification of one of these two bits re-
sets the interrupt request related to this interrupt
vector.
Bit 2:1 = PSM[1:0] Prescaler for Slow Mode
These bits are set and cleared by software. They
determine the CPU clock when the SMS bit is set
according to the following table.
Table 9. fCPU Value in Slow Mode
fCPU Value
fOSC / 4
fOSC / 16
fOSC / 8
fOSC / 32
PSM1
0
0
1
1
PSM0
0
1
0
1
Bit 0 = SMS Slow Mode Select
This bit is set and cleared by software.
0: Normal Mode - fCPU = fOSC/ 2
(Reset state)
1: Slow Mode - the fCPU value is determined by the
PSM[1:0] bits.
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