ST72331N4 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72331N4

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 256 EEPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS

STMicroelectronics 

Prev 21 22 23 24 25 26 27 28 29 30 Next

ST72E331 ST72T331

I/O PORTS (Cont’d)

Table 11. Port Configuration

Port

Pin name

PA0:PA2 1)

Input (DDR = 0)

OR = 0

OR = 1

floating*

pull-up with interrupt

Output (DDR = 1)

OR = 0

OR =1

open-drain

push-pull

Port A

PA3

floating*

pull-up with interrupt open-drain

push-pull

Port B

PA4:PA7

PB0:PB4

PB5:PB7 1)

floating*

floating*

floating*

pull-up with interrupt

pull-up with interrupt

open drain, high sink capability

open-drain

push-pull

open-drain

push-pull

Port C

PC0:PC7

floating*

pull-up

open-drain

push-pull

Port D

PD0:PD5

PD6:PD7 1)

floating*

floating*

pull-up

pull-up

open-drain

open-drain

push-pull

push-pull

Port E

PE0:PE1

PE4:PE7 1)

floating*

pull-up

floating*2)

open-drain

push-pull

open drain, high sink capability3)

Port F

PF0:PF2

PF4, PF6, PF7

floating*

floating*

pull-up with interrupt

pull-up

open-drain

open-drain

push-pull

push-pull

Notes:

1. ST72T331N only

2. For OTP/EPROM version, when OR=0: floating & when OR=1: reserved

3. For OTP/EPROM version, when OR=0: open-drain, high sink capability & when OR=1: reserved

* Reset state (The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value).

Warning: All bits of the DDR register which correspond to unconnected I/Os must be left at their reset value. They must

not be modified by the user otherwise a spurious interrupt may be generated.

30/107

30

Share Link: