ST72P361K9T3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST72P361K9T3' PDF : 224 Pages View PDF
ST72361
INTERRUPTS (Cont’d)
7.6.2 Register Description
EXTERNAL INTERRUPT CONTROL
REGISTER 0 (EICR0)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00
Bits 7:6 = IS3[1:0] ei3 sensitivity
The interrupt sensitivity, defined using the IS3[1:0]
bits, is applied to the ei3 external interrupts:
IS31 IS30
00
01
10
11
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 5:4 = IS2[1:0] ei2 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the ei2 external interrupts:
IS21 IS20
00
01
10
11
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 3:2 = IS1[1:0] ei1 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the ei1 external interrupts:
IS11 IS10
00
01
10
11
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 1:0 = IS0[1:0] ei0 sensitivity
The interrupt sensitivity, defined using the IS0[1:0]
bits, is applied to the ei0 external interrupts:
IS01 IS00
00
01
10
11
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
EXTERNAL INTERUPT CONTROL REGISTER 1
(EICR1)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0 TLIS TLIE
BIts 7:2 = Reserved
Bit 1 = TLIS Top Level Interrupt sensitivity
This bit configures the TLI edge sensitivity. It can
be set and cleared by software only when TLIE bit
is cleared.
0: Falling edge
1: Rising edge
Bit 0 = TLIE Top Level Interrupt enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Notes:
– A parasitic interrupt can be generated when
clearing the TLIE bit.
– In some packages, the TLI pin is not available. In
this case, the TLIE bit must be kept low to avoid
parasitic TLI interrupts.
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